The present invention relates to electronic data communications. More particularly, the disclosure relates to timing jitter and compensating for timing jitter in a high speed communication link.
The continual increase in processing speed and complexity provided by processors require tremendous amounts of information to be communicated between devices. The amount of information that is communicated can be increased by increasing the rate at which information is transmitted and by increasing the bus widths that carry the information. Early processors operated on eight bit buses carrying data at rates on the order of 1 MHz. Presently available processors operate on bus widths of 64 bits, each capable of supporting rates on the order of 1 Gigahertz. Further developments in processing capabilites allow even higher data rate to be supported on increasing numbers of data lines. Backplanes and circuit boards are increasingly required to support data rates on the order of 10 GHz. Additionally, high speed data communication is not limited to processor based circuits. Optical data links can be configured to operate at data rates on the order of 10 GHz.
The design of highly complex electronic communication devices is further complicated by the increasing desire to shrink or further miniaturize device sizes. Miniaturization requires that the circuits and devices be packed in highly dense structures.
Exceptional effort is focused on extending the data rate capabilities of economical copper backplanes. While VLSI circuit speed is steadily increasing, the wires between chips and even on-chip are becoming bottlenecks [R. Kollipara, et al., DesignCon2003(2003); R. Ho, et al., Proc. of the IEEE, vol. 89, no. 4, pp. 490-504 (2001)]. To avoid costly optical interconnects, circuit designers are forced to equalize the channel to increase the data rate, implement alternative channel coding schemes, or simply use more parallel channels J. Zerbe, et al., ISSCC Digest, pp. 80-81 (2003); V. Stojanovic and M. Horowitz, CICC 2003, pp. 589-594 (2003)]. Ultimately, space and power dissipation limits the number of parallel channels.
The trend in the design of Very Large Scale Integrated (VLSI) circuits and backplanes for computers is to push as many parallel data lines, called interconnects, into close proximity to achieve high physical densities. As parallel wires are positioned closer, electromagnetic energy couples between different interconnects. The energy coupled from one interconnect to another can be referred to as crosstalk. This crosstalk energy is related to the signal on the wire.
Increasing the interconnect density in controlled impedance environments is a problem common to copper backplane and VLS1. Electromagnetic coupling between transmission lines is overwhelming as trace separation reduces. To prevent an aggressive neighboring signal from generating errors in a victim signal, circuit designers match line lengths such that the strongest coupling from the aggressor occurs not in the center of the data eye but during data transitions. While this prevents errors at the sampling point, the aggressor generates jitter on the victim line.
Typically, the signal communicated across an interconnect is a digitally modulated signal. Therefore, the energy coupled from one interconnect to another depends on the symbols transmitted over the interconnects. The coupled energy from one interconnect can disturb the signal on neighboring interconnects. For example, the crosstalk energy can contribute to signal jitter on neighboring interconnects. Ultimately, the coupling can cause errors in data transmitted over the neighboring interconnects.
Crosstalk jitter introduces a sensitivity penalty to the performance of communication networks. The amount of energy coupled by crosstalk is further exacerbated by the use of pre-emphasis on the transmitted signal. Pre-emphasis is typically used to equalize the dispersive effect of the electrical interconnect. In typically pre-emphasis, the transmitted signal is amplified and distorted. Therefore, the transmitted pre-emphasized signal can create more crosstalk than signal transmitted without pre-emphasis.
Signal integrity issues such as timing jitter are at the forefront of high-speed digital design for communication applications. Electronic circuit speeds are overwhelming the legacy channels that traditionally could be treated as ideal.
In high-speed data circuits, the channel behavior is typically compensated appropriately to enable the highest information capacity. Noise considerations dictate the choice of equalization technique. Communications over densely packed high speed interconnects can benefit from techniques for minimizing the sources or effects of crosstalk in a serial communication interconnect.